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1 ? fn6762.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003-2006, 2008. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl6551irec zvs full bridge pwm controller the isl6551irec is a zero voltage switching (zvs) full bridge pwm controller designe d for isolated power systems. this part implements a unique control algorithm for fixed frequency zvs current mode control, yielding high efficiency with low emi. the two lower drivers are pwm-controlled on the trailing edge and employ resonant delay while the two upper drivers are driven at a fixed 50% duty cycle. this ic integrates many features in a 28 lead 6mmx6mm 2 qfn package to yield a complete and sophisticated power supply solution. control features include programmable soft- start for controlled start-up, programmable resonant delay for zero voltage switching, programmable leading edge blanking to prevent false triggering of the pwm comparator due to the leading edge spike of the current ramp, adjustable ramp for slope compensation, drive signals for implementing synchronous rectification in high output current, ultra high efficiency applications, and current share support for paralleling up to 10 units, which helps achieve higher reliability and availability as well as better thermal management. protective features include adjustable cycle- by-cycle peak current limiting fo r overcurrent protection, fast short-circuit protection (in hiccup mode), a latching shutdown input to turn off the ic completely on output overvoltage conditions or other extreme and undesirable faults, a non- latching enable input to accept an enable command when monitoring the input voltage and thermal condition of a converter, and vdd undervoltage lockout with hysteresis. additionally, the isl6551irec includes high current high- side and low-side totem-pole drivers to avoid additional external drivers for moderate gate capacitance (up to 1.6nf at 1mhz) applications, an uncommitted high bandwidth (10mhz) error amplifier for feedback loop compensation, a precision bandgap reference with 1.5% or 1% tolerance over recommended operating conditions, and a 5% ?in regulation? monitor. in addition to the isl6551ire c, other external elements such as transformers, pulse transformers, capacitors, inductors and schottky or synchronous rectifiers are required for a complete power supply solution. a detailed 200w telecom power supply reference design using the isl6551irec with companion intersil ics, supervisor and monitor isl6550 and half-bridge driver hip2100, is presented in application note an1002. in addition, the isl6551irec can also be designed in push- pull converters using all of the features except the two upper drivers and adjustable resonant delay features. features ? full traceability through assembly and test by date/trace code assignment ? enhanced process change notification per mil-prf-38535 ? enhanced obsolescence management ? high speed pwm (up to 1mhz) for zvs full bridge control ? current mode control compatible ? high current high-side and low-side totem-pole drivers ? adjustable resonant delay for zvs ? 10mhz error amplifier bandwidth ? programmable soft-start ? precision bandgap reference ? latching shutdown input ? non-latching enable input ? adjustable leading edge blanking ? adjustable dead time control ? adjustable ramp for slope compensation ? fast short-circuit protection (hiccup mode) ? adjustable cycle-by-cycle peak current limiting ? drive signals to implement synchronous rectification ? vdd undervoltage lockout ? current share support ? 5% ?in regulation? indication ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile applications ? full-bridge and push-pull converters ? power supplies for off-line and telecom/datacom ? power supplies for high end microprocessors and servers data sheet september 2, 2008
2 fn6762.0 september 2, 2008 pinout isl6551irec (28 ld qfn) top view ordering information part number part marking temp range (c) package pkg. dwg. # isl6551irec isl 6551ir 0 to +85 28 ld 6x6 qfn (pb-free) l28.6x6 ISL6551IR-TEC* isl 6551ir 0 to +85 28 ld 6x6 qfn (pb-free) l28.6x6 *please refer to tb347 for detai ls on reel specifications. rd ct vss vdd vddp1 vddp2 pgnd css eani eai eao share latsd dcok r_resdly r_ra isense pkilim bgref r_leb cs_comp upper1 upper2 lower1 lower2 sync1 sync2 on/off 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 isl6551irec
3 fn6762.0 september 2, 2008 functional pin description pin # pin symbol function 26 vss reference ground. all control circuits are referenced to this pin. 27 ct set the oscillator frequency, up to 1mhz. 28 rd adjust the clock dead time from 50ns to 1000ns. 1 r_resdly program the resonant delay from 50ns to 500ns. 2 r_ra adjust the ramp for slope compensation (from 50mv to 250mv). 3 isense the pin receives the current information via a current sense transformer or a power resistor. 4 pkilim set the overcurrent limit with the bandgap reference as the trip threshold. 5 bgref precision bandgap reference, 1.263v 2 % overall recommended operating conditions. 6 r_leb program the leading edge blanking from 50ns to 300ns. 7 cs_comp set a low current sharing loop bandwidth with a capacitor. 8 css program the rise time and the clamping voltag e with a capacitor and a resistor, respectively. 9 eani non-inverting input of error amp. it is clamped by the voltage at the css pin (vclamp). 10 eai inverting input of error amp. it receives the feedback voltage. 11 eao output of error amp. it is clamped by the voltage at the css pin (vclamp). 12 share this pin is the share bus connecting wi th other unit(s) for current share operation. 13 latsd the ic is latched off with a voltage greater t han 3v at this pin and is reset by recycling vdd. 14 dcok power-good indicati on with a 5% window. 15 on/off this is an enable pin that controls t he states of all drive signals and the soft-start. 16, 17 sync2, sync1 these are the gate control signals for the output synchronous rectifiers. 18, 19 lower2, lower1 both lower driver s are pwm-controlled on the trailing edge. 20, 21 upper2, upper1 both upper drivers are driven at a fixed 50% duty cycle. 22 pgnd power ground. high current return paths for both the upper and the lower drivers. 23, 24 vddp2, vddp1 power is delivered to both the upper and the lower drivers through these pins. 25 vdd power is delivered to all control circui ts including sync1 and sync2 via this pin. isl6551irec
4 fn6762.0 september 2, 2008 functional block diagram vss ct rd r_resdly r_ra isense pkilim bgref r_leb cs_comp eani eai eao 2 3 4 5 6 7 8 9 10 12 13 14 vdd vddp2 pgnd upper1 upper2 lower2 sync2 on/off dcok latsd share vddp1 lower1 sync1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 shutdown resodly ramp adjust clock generator pwm logic dc ok current share soft start uvlo shutdown latch bandgap reference shutdown soft- start shutdown latch resodly ramp adjust lower1 lower2 upper2 upper1 driver driver driver driver leb 1 css 11 (see fig. 4) external single poin t connection required circuits referenced to vss circuits referenced to pgnd error amp isl6551irec
5 fn6762.0 september 2, 2008 absolute maximum rati ngs thermal information supply voltage vdd, vddp1, vddp2 . . . . . . . . . . . . . . -0.3 to 16v enable inputs (on/off, latsd) . . . . . . . . . . . . . . . . . . . . . . . . vdd power good sink current (i dcok ) . . . . . . . . . . . . . . . . . . . . . . 5ma recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . 0c to +85c supply voltage range, vdd . . . . . . . . . . . . . . . . . . . 10.8v to 13.2v supply voltage range, vddp1 and vddp2 . . . . . . . . . . . . . <13.2v maximum operating junction temperature . . . . . . . . . . . . . . +125c thermal resistance ja (c/w) jc (c/w) qfn package (notes 1, 2). . . . . . . . . . 30 2.5 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379 for details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications these specifications apply for vdd = vddp = 12v and t a = 0c to +85c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. parameter symbol test conditions min typ max units supply (vdd, vddp1, vddp2) supply voltage vdd 10.8 12.0 13.2 v bias current from vdd idd vdd = 12v (not including drivers current at vddp) 5 13 18 ma total current from vdd and vddp icc vdd = vddp = 12v, f = 1mhz, 1.6nf load 60 ma undervoltage lockout (uvlo) start threshold vdd on 9.2 9.6 9.9 v stop threshold vdd off 8.03 8.6 8.87 v hysteresis vdd hys 0.3 1 1.9 v clock generator (ct, rd) frequency range f vdd = 12v (figure 1) 100 1000 khz dead time pulse width (note 3) dt vdd = 12v (figure 3) 50 1000 ns bandgap reference (bgref) bandgap reference voltage vref vdd = 12v, 399k pull-up, 0.1f, after trimming 1.250 1.263 1.280 v bandgap reference output current iref vdd = 12v, see ?block/pin functional descriptions? on page 9 for details 100 a pwm delays (note 3) low1, 2 delay ?rising? lowr with respect to resdly rising 5 ns low1, 2 delay ?falling? lowf compare delay @ verror = vramp 44 ns sync1, 2 delay ?falling? syncf with respect to resdly falling and with 20pf load 18 ns sync1, 2 delay ?rising? syncr with respec t to clk rising and with 20pf load 20 ns error amplifier (eani, eai, eao) (note 3) unity gain bandwidth ugbw 10 mhz dc gain dcg 79 db maximum offset error voltage vos 3.1 mv input common mode range vcm vdd = 12v 0.4 9 v common mode rejection ratio cmmr 82 db power supply rejection ratio pssr 1ma load 95 db maximum output source current isrc 2 ma isl6551irec
6 fn6762.0 september 2, 2008 maximum lower saturation voltage vsatlow sinking 0.27ma 125 mv ramp adjust (r_ra) (note 3) ramp frequency f 100 1000 khz linear voltage ramp, minimum lvr 50 mv linear voltage ramp, maximum 250 mv overall variation 25 % peak current limit (pkilim) peak current shutdown threshold ipkthr bgref = 0.1f, 399k pull-up 1.25 1.263 1.31 v peak current shutdown delay (note 3) ipkdel 75 ns soft-start (css) charge current iss vcss = 0.6v 8 12 a discharge current idis 1.6 5.2 ma cycle-by-cycle current limit vclamp 2 8 v drivers (upper1, upper2, lower1, lower2) maximum capacitive load (each) cl vdd = vddp = 12v, f = 1mhz, thermal dependence 1600 pf turn-on rise time t r 1.0nf capacitive load 8.9 16 ns turn-off fall time t f 1.0nf capacitive load 6.4 10 ns shutdown delay (note 3) t sd 1.0nf capacitive load 14.5 ns rising edge delay (note 3) t rd 1.0nf capacitive load 16.4 ns falling edge delay (note 3) t fd 1.0nf capacitive load 13.7 ns vsat_sourcing vsat_high sourcing 20ma 1.00 v sourcing 200ma 1.35 v vsat_sinking vsat_l ow sinking 20ma 0.035 v sinking 200ma 0.31 v synchronous signals (sync1, sync2) maximum capacitive load vdd = 12, f = 1mhz 20 pf programmable delays (resdly, leb) (note 3) resonant delay adjust range (figure 7) 50 500 ns resonant delay t resdly r_resdly = 10k 55 ns r_resdly = 120k 488 ns leading edge blanking adjust range (figure 8) 50 300 ns leading edge blanking t leb r_leb = 20k 64 ns r_leb = 140k 302 ns r_leb = 12v 0 ns latching shutdown (latsd) fault threshold vin 3 v fault_not threshold vinn 1.9 v time to set latch (note 3) t set 415 ns on/off (onoff) turn-off threshold off 0.8 v turn-on threshold on 2 v electrical specifications these specifications apply for vdd = vddp = 12v and t a = 0c to +85c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. (continued) parameter symbol test conditions min typ max units isl6551irec
7 fn6762.0 september 2, 2008 current share (share, cs_comp) (note 3) voltage offset between error amp voltage of master and slave vcs_offset share = 30k 30 mv maximum source current to external reference ics_source share = 30k 190 a maximum correctable deviation in reference voltage between master and slave share = 30k, rsource = 1k, output reference = 1 to 5v, (see figure 10) 190 mv share/adjust loop bandwidth cs bw cs_comp = 0.1f 500 hz dc ok (dcok) sink current i dcok 5ma saturation voltage v satdcok i dcok = 5ma 0.4 v input reference vref_in 1 5 v threshold (relative to vref_in) ov (figure 11) 5 % recovery (relative to vref_in) ov (figure 11) 3 % threshold (relative to vref_in) uv (figure 11) -5 % recovery (relative to vref_in) uv (figure 11) -3 % transient rejection (note 3) trej 100mv transient on vout (system implicit rejection and feedback network dependence (figure 12) 250 s note: 3. limits established by characterization and are not production tested. electrical specifications these specifications apply for vdd = vddp = 12v and t a = 0c to +85c, unless otherwise stated. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperature limits established by characteri zation and are not production tested. (continued) parameter symbol test conditions min typ max units isl6551irec
8 fn6762.0 september 2, 2008 drive signals timing diagrams timing diagram descriptions the two upper driv ers (upper1 and upper2) are driven at a fixed 50% duty cycle and t he two lower drivers (lower1 and lower2) are pwm-controlled on the trailing edge, while the leading edge employs resonant delay (t2 and t4). in current mode control, t he sensed switch (fet) current (i lower1 and i lower2 ) is processed in the ramp adjust and leading edge blanking (leb) circuits and then compared to a control signal (eao). spik es, due to parasitic elements in the bridge circuit, would falsely trigger the comparator generating the pwm signal. to prevent false triggering, the leading edge of the sensed current signal is blanked out by t1, which can be programmed at the r_leb pin with a resistor. internal switches gate the analog input to the pwm comparator, implementing the blanking function that eliminates response degrading delays, which would be caused if filtering of the curr ent feedback was incorporated. the dead time (t3 and t5) is the delay to turn on the upper fet (upper1/upper2) after its corresponding lower fet (lower1/lower2) is turned off when the bridge is operating at maximum duty cycle in normal conditions, or is responding to load transients or input line dipping conditions. therefore, the upper and lower fets that are located at the same side of the bridge can never be turned on together, which eliminates shoot-through currents. sync1 and sync2 are the gate control signals for the out put synchronous rectifiers. they are biased by vdd and are capable of driving capacitive loads up to 20pf at 1mhz clock frequency (500khz switching frequency). external drivers wit h high current capabilities are required to drive the synchronous rectifiers, cascading with both synchronous signals (sync1 and sync2). clock upper1 upper2 sync1 sync2 lower1 i lower1 ramp adjust output to pwm logic t1 t2 t3 t4 t5 t1 = leading edge blanking t2 = t4 = resonant delay t3 = t5 = dead time in the above figure, the values for t1 thr ough t5 are exaggerated for demonstration purposes. lower2 notes: eao i lower2 eao eao isl6551irec
9 fn6762.0 september 2, 2008 shutdown timing diagrams shutdown timing descriptions a (on/off) when the on/off is pulled low, the soft-start capacitor is discharged and all the drivers are disabled. when the on/off is released without a fault condition, a soft-start is initiated. b (overcurrent) if the output of the converter is over loaded, i.e., the pkilim is above the bandgap reference voltage (bgref), the soft- start capacitor is discharged very quickly and all the drivers are turned off. thereafter, the soft-start capacitor is charged slowly, and discharged quickly if the output is overloaded again. the soft-start will remain in hiccup mode as long as the overload conditions persist. once the overload is removed, the soft-start capacitor is charged up and the converter is then back to normal operation. c (latching shutdown) the ic is latched off completely as the latsd pin is pulled high, and the soft-start capacitor is reset. d (on/off) the latch cannot be reset by the on/off. e (latch reset) the latch is reset by removing the vdd. the soft-start capacitor starts to be charged after vdd increases above the turn-on threshold vdd on . f (vdd uvlo) the ic is turned off when the vdd is below the turn-off threshold vdd off . hysteresis vdd hys is incorporated in the undervoltage lockout (uvlo) circuit. block/pin functional descriptions detailed descriptions of each individual block in the functional block diagram on page 3 are included in this section. application informat ion and design considerations for each pin and/or each block are also included. ic bias power (vdd, vddp1, vddp2) ? the ic is powered from a 12v 10% supply. ? vdd supplies power to both the digital and analog circuits and should be bypassed dire ctly to the vss pin with an 0.1f low esr ceramic capacitor. latsd on/off ilim_out soft-start driver soft-start pkilim < bgref pkilim > bgref shutdown fault fault off overcurrent latched off/on latch undervoltage vdd on vdd off latch reset by vdd a b c d e f enable reset lockout removing vdd latch cannot be reset by on/off isl6551irec
10 fn6762.0 september 2, 2008 ? vddp1 and vddp2 are the bias supplies for the upper drivers and the lower drivers, respectively. they should be decoupled with ceramic capacitors to the pgnd pin. ? heavy copper should be attached to these pins for a better heat spreading. ic gnds (vss, pgnd) ? vss is the reference ground, the return of vdd, of all control circuits and must be kept away from nodes with switching noises. it should be connected to the pgnd in only one location as close to the ic as practical. for a secondary side control system, it should be connected to the net after the output capacitors, i.e., the out put return pinout(s). for a primary side control system, it sh ould be connected to the net before the input capacitors, i.e ., the input return pinout(s). ? pgnd is the power return, the hi gh-current return path of both vddp1 and vddp2. it should be connected to the source pins of two lower power switches or the returns of external drivers as close as possib le with heavy copper traces. ? copper planes should be attached to both pins. undervoltage lockout (uvlo) ? uvlo establishes an orderly start-up and verifies that vdd is above the turn-on threshold voltage (vdd on ). all the drivers are held low during the lockout. uvlo incorporates hysteresis vdd hys to prevent multiple startup/shutdowns while powering up. ? uvlo limits are not applicable to vddp1 and vddp2. bandgap reference (bgref) ? the reference voltage vref is generated by a precision bandgap circuit. ? this pin must be pulled up to vdd with a resistance of approximately 399k for proper operation. for additional reference loads (no more than 1ma), this pull-up resistor should be scaled accordingly. ? this pin must also be decoupled with an 0.1f low esr ceramic capacitor. clock generator (ct, rd) ? this free-running oscillator is set by two external components, as shown in figure 2. a capacitor at ct is charged and discharged with two equal constant current sources and fed into a window comparator to set the clock frequency. a resistor at rd sets the clock dead time. rd and ct should be tied to the vss pin on their other ends as close as possible. the corresponding ct for a particular frequency can be selected from figure 1. ? the switching frequency (fsw) of the power train is half of the clock frequency (fclock), as shown in equation 1. fsw fclock 2 ------------------- = (eq. 1) figure 1. ct vs frequency 3,000 2,500 2,000 1,500 1,000 500 0 10 100 10,000 ct (pf) recommended range f ( khz ) +0 c +60 c +120c 1,000 set clock dead time (dt) rd rd ct ct vmax vmin vdd - - + - + out out s r q q q clk clk q dt dt figure 2. simplified clock generator circuit i_ct i_ct isl6551irec
11 fn6762.0 september 2, 2008 ? note that the capacitance of a scope probe (~12pf for single-ended) would induce a smaller frequency at the ct pin. it can be easily seen at a higher frequency. an accurate operating frequency can be measured at the outputs of the bridge/ synchronous drivers. the dead time is the delay to turn on the upper fet (upper1/upper2) after its corresponding lower fet (lower1/lower2) is turned off when the bridge is operating at maximum duty cycle in normal conditions, or is responding to load transients or input line dipping conditions. this helps to prevent shoot through between the upper fet and the lower fet that are located at the same side of the bridge. the dead time can be estimated using equation 2: where m = 11.4 (vdd = 12v), 11.1(vdd = 14v), and 12 (vdd = 10v), and rd is in k . this relationship is shown in figure 3. error amplifier (eai, eani, eao) ? this amplifier compares the feedback signal received at the eai pin to a reference signal set at the eani pin and provides an error signal (eao) to the pwm logic. the feedback loop compensation can be programmed via these pins. ? both eani and eao are clamped by the voltage (vclamp) set at the css pin, as shown in figure 5. note that the diodes in the functional block diagram represent the clamp function of the css in a simplified way. soft-start (css) ? the voltage on an external capacitor charged by an internal current source i ss is fed into a control pin on the error amplifier. this causes the er ror amplifier to: 1) limit the eao to the soft-start voltage level; and 2) over-ride the reference signal at the eani with the soft-start voltage, when the eani voltage is higher than the soft-start voltage. thus, both the output voltage and current of the power supply can be controlled by the soft-start. ? the clamping voltage determines the cycle-by-cycle peak current limiting of the power supply. it should be set above the eani and eao voltages and can be programmed by an external resistor, as shown in figure 5 using equation 3. ? per equation 3, the clamping vo ltage is a function of the charge current iss. for a more predictable clamping voltage, the css pin can be connected to a reference based clamp circuit, as shown in figure 4. to make the vclamp less dependent on the soft-start current (iss), the currents flowing through r1 and r2 should be scaled much greater than iss. the rela tionship of this circuit can be found in equation 4. ? the soft-start rise time (t ss ) can be calculated with equation 5. the rise time (t rise ) of the output voltage is approximated with equation 6. drivers (upper1, upper2, lower1, lower2) ? the two upper drivers are driv en at a fixed 50% duty cycle and the two lower drivers are pwm-controlled on the trailing edge while the leading edge employs resonant delay. they are biased by vddp1 and vddp2, respectively. ? each driver is capable of drivin g capacitive loads up to cl at 1mhz clock frequency and higher loads at lower frequencies on a layout with high effective thermal conductivity. ? the uvlo holds all the drivers low until the vdd has reached the turn-on threshold vdd on . ? the upper drivers require assistance of external level-shifting circuits, such as intersil?s hip2100 or pulse transformers to drive the upper power switches of a bridge converter. dt mrd k ------------------- - = (eq. 2) (ns) figure 3. rd vs dead time (vdd = 12v) dead time (s) 2.0 1.6 1.2 0.8 0.4 0 0 20 40 60 80 100 120 140 160 rd (k ) vclamp rcss iss ? = (eq. 3) (v) figure 4. reference-based clamp circuit v ref r1 css r2 (eq. 4) vclamp iss r1 r2 r1 r2 + ---------------------- ? vref r2 r1 r2 + ---------------------- ? + t ss vclamp css iss --------------------------------------- = (s) (eq. 5) t rise eani css iss -------------------------------- = (s) (eq. 6) isl6551irec
12 fn6762.0 september 2, 2008 peak current limit (pkilim) ? when the voltage at pkilim exceeds the bgref voltage, the gate pulses are terminated and held low until the next clock cycle. the peak current limit circuit has a high-speed loop with propagation delay ipkdel. peak current shutdown initiates a soft-start sequence. ? the peak current shutdown threshold is usually set slightly higher than the normal cycle- by-cycle pwm peak current limit (vclamp) and t herefore will normally only be activated in a short-circuit condition. the limit can be set with a resistor divider from the isense pin. the resistor divider relationship is defined in equation 7. ? in general, the trip point is a little smaller than the bgref due to the noise and/or ripple at the bgref. latching shutdown (latsd) ? a high ttl level on latsd latches the ic off. the ic goes into a low power mode and is reset only after the power at the vdd pin is removed completely. the on/off cannot reset the latch. ? this pin can be used to latch the power supply off on output overvoltage or other undesired conditions. on/off (on/off) ? a high standard ttl input (safe also for vdd level) signals the controller to turn on. a low ttl input turns off the controller and terminates all drive signals including the sync outputs. the soft-start is reset. ? this pin is a non-latching input and can accept an enable command when monitoring the input voltage and the thermal condition of a converter. resonant delay (r_resdly) ? a resistor tied between r_resdly and vss determines the delay that is required to turn on a lower fet after its corresponding upper fet is turned off. this is the resonant delay, which can be estimated with equation 8. ? figure 7 illustrates the relationsh ip of the value of the resistor (r_resdly) and the resonant delay (t resdly ). the percentages in the figure are the tolerances at the two end points of the curve. leading edge blanking (r_leb) ? in current mode control, the sensed switch (fet) current is processed in the ramp adjust and leb circuits and then compared to a control signal (eao voltage). spikes, due to parasitic elements in the bridge circuit, would falsely trigger the comparator generating the pwm signal. to prevent false triggering, the leading edge of the sensed current signal is blanked out by a period that can be programmed with the r_leb resistor. internal switches gate the analog input to the pwm comparator, implementing the blanking function that css vdd iss shutdown 400mv + - ssl (to blanking circuit) error amp eao eai (?) eani (+) figure 5. simplified clamp/soft-start r css (see fig. 9) figure 6. peak current limit set circuit r up r down isense pkilim rdown rdown rup + -------------------------------------- bgref isense max () ----------------------------------------- = (eq. 7) (eq. 8) t resdly = 4.01 x r_resdly/k + 13 (ns) t resdly (ns) 500 450 400 350 300 250 200 150 100 50 0 20 40 60 80 100 120 +37% +4% -24% figure 7. r_resdly vs resdly r_resdly (k ) +18% isl6551irec
13 fn6762.0 september 2, 2008 eliminates response degrading delays which would be caused if filtering of the cu rrent feedback was incorporated. the current ramp is blanked out during the resonant delay period because no switching occurs in the lower fets. the leading edge blanking function will not be activated until the soft-start (css) reaches over 400m v, as illustrated in figures 5 and 9. the leading edge blanking (leb) function can be disabled by tying the r_leb pin to vdd, i.e., leb = 1. never leave the pin floating. ? the blanking time can be estimated with equation 9, whose relationship can be seen in figure 8. the percentages in the figure are the tolerances at th e two endpoints of the curve. ramp adjust (r_ra, isense) ? the ramp adjust block adds an offset component (200mv) and a slope adjust component to the isense signal before processing it at the pwm logic block, as shown in figure 9. this ensures that the ramp voltage is always higher than the oags (ground sensing op amp) minimum voltage to achieve a ?zero? state. ? it is critical that the input signal to isense decays to zero prior to or during the clock dead time. the level-shifting and capacitive summing circ uits in the ramp adjust block are reset during the dead time. any input signal transitions that occur after th e rising edge of clk and prior to the rising edge of resdly can cause severe errors in the signal reaching the pwm comparator. ? typical ramp values are hundreds of mv over the period on a 3v full scale current. too much ramp makes the controller look like a voltage mode pwm, and too little ramp leads to noise issues (jitter). the amount of ramp (vramp), as shown in figure 9, is programmed with the r_ra resistor and can be calculated with equation 10. where dt = duty cycle/fsw - t leb (s). duty cycle is discussed in detail in application note an1002. ? the voltage representation of the current flowing through the power train at isense pin is normally scaled such that the desired peak current is less than or equal to vclamp-200mv-vramp, where the clamping voltage is set at the css pin. (eq. 9) t leb = 2 x r_leb / k + 15 (ns) figure 8. r_leb vs t leb +20% -18% +51% -11% 300 250 200 150 100 50 0 20 40 60 80 100 120 140 t leb (ns) r_leb (k ) (eq. 10) v ramp = bgref x dt /(r_ra x 500e-12) (v) add ramp 399k bgref vdd blank 0.1 r_ra r_ra isense 200mv + - resdly leb ssl adj_ramp ramp_out (to pwm comparator) 200mv 0 ramp_out 200mv adj_ramp isense resdly leb ssl ramp_out 0xxblank x00blank 1 1 x no blank 1 x 1 no blank figure 9. simplified ramp adjust and leading edge blanking circuits (see fig. 4) set blanking time r_leb r_leb isl6551irec
14 fn6762.0 september 2, 2008 sync outputs (sync1, sync2) ? sync1 and sync2 are the gate control signals for the output synchronous rectifiers. they are biased by vdd and are capable of driving capacitive loads up to 20pf at 1mhz clock frequency (500khz switching frequency). these outputs are turned off so oner than the turn-off at upper1 and upper2 by the clock dead time, dt. ? inverting both sync signals or both lower signals is another possible way to control the drivers of the synchronous rectifiers. when using these drive schemes, the user should understand the issues that might occur in his/her applications, especially the impacts on current share operation and light load operation. refer to application note an1002 for more details. ? external high current drivers controlled by the synchronous signals are required to drive the synchronous rectifiers. a puls e transformer is required to pass the drive signals to the secondary side if the ic is used in a primary control system. share support (share, cs_comp) ? the unit with the highest reference is the master. other units, as slaves, adjust their re ferences via a source resistor to match the master reference sharing the load current. the source resistor is typically 1k connecting the eani pin and the output reference (external reference or bgref), as shown in figure 10. the share bus represents a 30k resistive load per unit, up to 10 units. ? the output (adj) of ?o perational transconductance amplifier (ota)? can only pull high and it is floating while in master mode. this ensures that no current is sourced to the output reference when the ic is working by itself. ? the slave units attempt to drive their error amplifier voltage to be within a pre-dete rmined offset (30mv typical) of the master error voltage (the share bus). the current- share error is nominally (30mv/eao)*100% assuming no other source of error. with a 2.5v full load error amp voltage, the current-share error at full load would be -1.2% (slaves relative to master). ? the bandwidth of the current sharing loop should be much lower than that of the voltage loop to eliminate noise pick- up and interactions between the voltage regulation loop and the current loop. a 0.1f capacitor is recommended between cs_comp and vss pins to achieve a low current sharing loop bandwidth (100hz to 500hz). power-good (dcok) ? dcok pin is an open drain output capable of sinking 5ma. it is low when the output voltage is within the uvov window. the static regulation limit is 3%, while the 5% is the dynamic regulation limit. it indicates power-good when the eai is within -3% to +5% on the rising edge and within +3% to -5% on the falling edge, as shown in figure 11. ? the dcok comparator might not be triggered even though the output voltage exceeds 5% limits at load transients. this is because the feedback net work of the error amplifier filters out part of the transients and the eai only sees the remaining portion that is still within the limits, as illustrated in figure 12. the lower the ?zero (1/rc)? of the error amplifier, the larger the portion of the transient that is filtered out. thermal pad (in qfn only) ? in the qfn package, the p ad underneath the center of the ic is a ?floating? thermal substrate. the pcb ?thermal land? design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). this combination of vias for vertical heat escape and buried planes for heat spreading allows the qfn to achieve its full thermal potential. this pad should be connected to a low noise copper plane such as vss. ? refer to tb389 for design guidelines. - + ota adj + - + - eao cs_comp 0.1 f 1k output eani (+) share 30k 30mv figure 10. simplified current share circuit reference figure 11. undervoltage-overvoltage window dcok fault -5% -3% eani +3% +5% eai isl6551irec
15 fn6762.0 september 2, 2008 additional applications information table 11 highlights parameter setting for the isl6551irec. designers can use this table as a design checklist. for detailed operation of the isl6551irec, see ?block/pin functional descriptions? on page 9. figure 13 shows the block diagram of a power supply system employing the isl6551irec full bridge controller. the isl6551irec not only is a full bridge pwm controller but also can be used as a push-pull pw m controller. users can design a power supply by selecting appropriate blocks in the system blocks chart based on the pow er system requirements. figures 13a, 14a, 15a, 16a, 17a, 18a, 19, 20a, 21, 22a, and 24a have been used in the 200w telecom power supply reference design, which can be found in the application note an1002. to meet the specific ations of the power supply, minor modifications of each block are required. to take full advantage of the integrated features of the isl6551irec, ?secondary side control? is recommended. figure 12. output transient rejection eani eai vout eao vout eai 0.90v 1.00v 1.10v 1.00v 0.95v 1.05v 15n 18k 1k - + r c table 1. parameter setting highlights/checklist parameter pin name formula or setting highlight unit figure # frequency ct set 50% duty cycle pulses with a fixed frequency khz 1, 2 dead time rd dt = mxrd/k , where m = 11.4 ns 3 resonant delay r_resdly t resdly = 4.01xr_resdly/k + 13 ns 7 ramp adjust r_ra vramp = bgref/(r_rax500e-12)xdt v - current sense isense 3v v - power-good dcok 5% with hysteresis, sink up to 5ma, transient rejection v 11, 12 ic enable on/off turn on/off at ttl level v - reference ground vss connect to pgnd in only one single point - - power ground pgnd single point to vss plane - - upper drivers upper1, upper2 capacitive load up to 1.6nf at fsw = 500khz - - lower drivers lower1, lower2 capacitive load up to 1.6nf at fsw = 500khz - - synchronous drive signals sync1, sync2 capaci tive load up to 20pf at fsw = 500khz - - bias for control circuits vdd 12v 10%, 0.1f decoupling capacitor v - biases for bridge drivers vddp1, vddp2 need decoupling capacitors v - note: vdd = 12v at room temperature, unless otherwise stated. isl6551irec
16 fn6762.0 september 2, 2008 system blocks chart input filters general input capacitors are required to absorb the power switch (fet) pulsating currents. emi for good emi performance, the ripple current that is reflected back to the input line can be reduced by an input l-c filter, which filters the differential-mode noises and operates at two times the switching frequency, i.e., the clock frequency (fclock). in some cases, an additional common-mode choke might be required to filter the common-mode noises. current sense two-leg sense senses the current that flows through both lower primary fets. operates at the switching frequency. top sense senses the sum of the current that flows through both upper primary fets. operates at the clock frequency. figure 13a. general figure 13b. emi figure 13. block diagram of a power su pply system using isl6551irec controller biases rectifiers output filter v out feedback isl6551irec controller primary fets primary bias secondary bias current v in input filter supervisor circuits main transformer sense drivers secondary primary fet drivers v in f v in c in v in v in f l in c in figure 14a. two-leg sense figure 14b. top sense figure 14c. resistor sense (primary control) isense t_current q3_s q4_s isense v in f current_sen_p isense rsense q3_s and q4_s isl6551irec
17 fn6762.0 september 2, 2008 resistor sense this simple scheme is used in a primary side control system. the sum of the current that fl ows through both lower primary fets is sensed with a low impedance power resistor. the sources of q3 and q4 and isense should be tied at the same point as close as possible. biases linear regulator - in a primary side control system, a linear regulator derived from the input line can be used for the start-up purpose, and an extra winding coupled with the main transformer can provide the controller power after the start-up. dcm flyback - use a pwm controller to develop both primary and secondary biases with discontinuous current mode flyback topology. primary fets full bridge four mosfets are required for full bridge converters. the drain to source voltage rating of the mosfets is vin. push-pull only the two lower mosfets are required for push-pull converters. the two upper drivers are not used. the v ds of the mosfets is 2xvin. feedback secondary control in secondary side control system s, only a few resistors and capacitors are required to complete the feedback loop. primary control this feedback loop configuration for primary side control systems requires an optocoupl er for isolation. the bandwidth is limited by the optocoupler. rectifiers figure 15a. full bridge figure 15b. push-pull q3_g p? q1_g q3_s q1 q3 q2_g p+ q4_g q2 q4 q4_s v in f or current_sen_p p1? q3_g q3_s q3 q4_g p2? q4_s q4 figure 16a. secondary control figure 16b. primary control figure 17a. current doubler rectifiers eao eai vopout vopout il207 tl431 vref = 5v eai eao synchronous fets schottky s+ synp synn s+ s? s? isl6551irec
18 fn6762.0 september 2, 2008 current doubler rectifiers 1. synchronous fets are used for low output voltage, high output current and/or high efficiency applications. 2. schottky diodes are used for lower current applications. pins s+ and s- are connected to the output filter and the main transformer with current doubler configurations. conventional rectifiers 1. synchronous fets are used for low output voltage, high output current and/or high efficiency applications. 2. schottky diodes are used for lower current applications. pins s+ and s- are connected to the main transformer with conventional configurations. self-driven rectifiers for low output voltage applicati ons, both fets can be driven by the voltage across the secondary winding. this can work with all kinds of main transforme r configurations, as shown in figures 18a, 18b, 18c and 18d. main transformers full bridge and current doubler no center tap is required. the secondary winding carries half of the load, i.e., only half of the load is reflected to the primary. conventional full bridge center tap is required on the secondary side, and no center tap is required on the primary side. the secondary winding carries all the load. i.e., all the load is reflected to the primary. push-pull and current doubler center tap is required on the primary side, and no center tap is required on the secondary side. the secondary winding carries half of the load, i.e., on ly half of the load is reflected to the primary. conventional push-pull both primary and secondary sides require center taps. the secondary winding carries all the load, i.e., all the load is reflected to the primary. supervisor circuits integrated solution ? intersil isl6550 supervisor and monitor (sam). ? over-temperature protection (discrete) ? input uv lockout (discrete) figure 17b. conventional rectifiers figure 17c. self-driven rectifiers figure 18a. full bridge and current doubler figure 18b. conventional full bridge s+ s? synn synp synchronous fets schottky s? s+ s+ s? p+ p? s + s? p+ p? s + v out f s? figure 18c. push-pull and current doubler figure 18d. conventional push-pull s + v in f or s? p1? p2? current_sen_p s + v out f s? v in f or p1? p2? current_sen_p 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 vcc vopp vopm vopout vref5 gnd ovuvth bdac dachi daclo uvdly pgood start pen ovuvsen vid0 vid1 vid2 vid3 vid4 pgood start pen bdac vref5 vopout figure 19. isl6550 isl6551irec
19 fn6762.0 september 2, 2008 discrete solution ? differential amplifier ? vcc undervoltage lockout ? programmable output ov and uv ? programmable output ? status indicators (pgood and start) ? precision reference ? over- temperature protection ? input uv lockout the integrated solution is much simpler than a discrete solution. over-temperature protection and input undervoltage lockout can be added for better system protection and performance. the discrete solution requires a significant number of components to implement the f eatures that the isl6550 can provide. output filter current doubler filter - two inductors are needed, but they can be integrated and coupled into one core. each inductor carries half of the load operat ing at the switching frequency. conventional filter - one inductor is needed. the inductor carries all the load operating at two times the switching frequency. controller isl6551irec controller it can be used as a full bridge or push-pull pwm controller. the qfn package requires less space. secondary drivers figure 20a. current doubler filter figure 20b. conventional filter vout s+ s? l out c out v out f l out f clock c out v out figure 22a. inverting drivers figure 22b. non-inverting drivers figure 22c. primary control vss ct rd r_resdly r_ra isense pkilim bgref r_leb cs_comp css eani eai eao vdd vddp2 pgnd upper1 upper2 lower2 sync2 on / off dcok lstsd share vddp1 lower1 sync1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 isl6551 led output eai eao lstsd input uv and ov share figure 21. isl6551irec controller reference bus (bdac) in gnd sync2 /lower1 sync1 /lower2 mic4421bm out out in gnd synp synn mic4421bm mic4422bm sync2 mic4422bm synn in out gnd sync1 synp in out gnd syn1 syn2 f sw t_syn in out gnd in out gnd synp synn isl6551irec
20 fn6762.0 september 2, 2008 inverting drivers inverting the sync signals or the lower signals with external high current drivers to drive the synchronous fets. non-inverting drivers cascading sync signals with non-inverting high current drivers to drive the synchronous fets. there is a dead time between sync1 and sync2. for a higher efficiency, schottky diodes are normally in parallel with the synchronous fets to reduce the conduction losses during the dead time in high output current applications. primary control this requires a pulse transforme r, operating at the switching frequency, for isolation. there are three options to drive the synchronous fets, as described in previous lines. primary fet drivers push-pull drivers push-pull medium current drivers upper drivers are not used. no external drivers are required. secondary control. operate at the switching frequency. push-pull high current drivers upper drivers are not used. exte rnal high current drivers are required and less power is dissipated in the isl6551irec controller. secondary control. operate at the switching frequency. push-pull primary control upper drivers are not used. both lower drivers can directly drive the power switches. external drivers are required in high gate capacitance applications. inverting non inverting syn1 sync2/lower1 sync1 syn2 sync1/lower2 sync2 ic mic4421bm mic4422bm figure 23a. push-pull medium current drivers figure 23b. push-pull high current drivers figure 23c. push-pull primary control lower1 lower2 q3_s q4_s q4_g q3_g hi li vss ho hs lo lower1 lower2 q3_g q3_s q4_s hip2100ib q4_g hi hs lo li vss hip2100ib q3_g q3_s q4_g q4_s lower1 lower2 pgnd ho isl6551irec
21 fn6762.0 september 2, 2008 full bridge drivers full bridge high current drivers external high current drivers are required and less power is dissipated in the isl6551irec co ntroller. secondary control. operate at the s witching frequency. full bridge medium current drivers no external drivers are requir ed. secondary control. operate at the switching frequency. full bridge primary control lower drivers can directly dr ive the power switches, while upper drivers require the assistance of level-shifting circuits such as a pulse transformer or intersil?s hip2100 half-bridge driver. external high current drivers are not required in medium power applications, but level-shifting circuits are still required for upper drivers. oper ate at the switching frequency. figure 24a. full bridge high current drivers figure 24b. full bridge medium current drivers figure 24c. full bridge primary control upper1 upper2 q1_g p? q3_g q3_s hip2100ib hi li vss ho hs lo q2_g p+ q4_g q4_s hip2100ib lower1 lower2 hi li vss ho hs lo lower1 lower2 q3_g q3_s q4_s q4_g upper1 upper2 q1_g p? p+ q2_g hi li vss ho hs lo q2_g p+ q4_s lower2 upper2 hip2100ib pgnd hi li vss ho hs lo q1g p? q3_g q3_s hip2100ib upper1 lower1 pgnd ho hs lo q4_g isl6551irec
22 fn6762.0 september 2, 2008 simplified typical a pplication schematics 1.263v lower2 lower1 lower1 upper1 upper1 sync2 upper2 share bus sa+12v upper2 3.3vout pgnd sb+48v sa+12v sa+12v sb+12v sb+12v lower2 sa+12v pgood lower2 sync1 sync2 lower1 sync1 led hip2100 hip2100 isl6551 isl6550 mic4421 mic4421 vs nc gnd gnd out out in vs vcc vopp vopm vopout gnd bdac ovuvsen pgood vid0 pen uvdly start vid1 ovuvth vref5 dachi daclo vid2 vid3 vid4 1 2 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 19 20 vdd ho hs hi li vss hb lo - + vs nc gnd gnd out out in vs + - v+ v- out vss rd ct r_resdly r_ra isense pkilim bgref r_leb cs_comp css eani eai eao share latsd dcok sync2 on/off sync1 lower2 lower1 upper2 upper1 pgnd vddp2 vddp1 vdd 1 2 3 4 5 6 7 8 9 10 12 11 14 13 24 23 22 21 20 19 18 17 16 15 25 26 27 28 vdd ho hs hi li vss hb lo 200w telecommunication power supply (see an1002 for details) isl6551irec
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6762.0 september 2, 2008 isl6551irec quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l28.6x6 28 lead quad flat no-lead plastic package (compliant to jedec mo-220vjjc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 6.00 bsc - d1 5.75 bsc 9 d2 3.95 4.10 4.25 7, 8 e 6.00 bsc - e1 5.75 bsc 9 e2 3.95 4.10 4.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n282 nd 7 3 ne 7 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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